Recently, accompanied with miniaturization and sophistication of an electronic device, a technique for improving a packaging density of a semiconductor device mounted on the electronic device has been developed. Various kinds of the semiconductor device with the stack structure having a plurality of semiconductor chips stacked have been developed as a high packaging density technique.
Japanese Patent Application Publication No. 2002-50738 (Document 1) and Japanese Patent Application Publication No. 2005-19521 (Document 2) disclose the semiconductor device in which a through hole is formed in the semiconductor chip, and a through electrode separated from the semiconductor chip with the insulation member is disposed inside the through hole. The aforementioned semiconductor device may be electrically coupled with another semiconductor device or the interposer with the solder ball applied onto the connection electrode of the semiconductor chip.
In the semiconductor device disclosed in Documents 1 and 2, the step of forming the through electrode for connecting interconnections on the upper and the lower surfaces of the semiconductor chip is performed independently of the step of forming the solder ball for connecting the semiconductor chip to another semiconductor device or the interposer, resulting in the complicated manufacturing step and the increased manufacturing cost.